The number of write operations which can be performed on a single memory cell of a memory device such as a NAND flash memory and a phase-change random access memory (PCRAMs) is limited. For example, the number of write operations in a typical PCRAM may be limited to a range of from about 106 to about 108 operations. Accordingly, the life span of a memory device may be drastically reduced when the write operations are concentrated on a specific cell or cell region. To prevent the concentration of the write operations on a specific cell or cell region of a memory device, a wear leveling operation is typically performed to even out the performance of the write operations on all of the cell regions of the memory device. A widely used method for wear leveling achieves a more even allocation of the write operations between all of the cell regions of the memory device by changing the address mapping between logical and physical addresses.
Memory devices may include a plurality of memory regions known as memory blocks. When the number of write operations for a memory block exceeds a threshold value or when a memory block has a physical defect then the memory bloc can no longer operate normally and may generate too many errors. Heretofore, typically, such memory blocks are identified as bad memory block and are excluded from any further read and write operations.